Design Summary: "run_benchmark"

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Full run_benchmark Metrics

- units import_verilog0 syn0 floorplan0 place0 cts0 route0 write_gds0 write_data0
errors 0 0 0 0 0 0 0 0
warnings 60 119 41 42 40 40 0 40
drvs --- --- --- 14 14 147 --- 121
drcs --- --- --- --- --- 0 --- ---
unconstrained --- --- 817 817 817 817 --- 817
cellarea um^2 --- 1416.855 1383.960 1492.200 1492.200 1492.200 --- 1492.200
totalarea um^2 --- --- 3531.570 3531.570 3531.570 3531.570 --- 3531.570
utilization % --- --- 39.188 42.253 42.253 42.253 --- 42.253
logicdepth --- --- 0 0 0 0 --- 0
peakpower mw --- --- 0.001 0.001 0.001 0.001 --- 0.001
leakagepower mw --- --- 0.001 0.001 0.001 0.001 --- 0.001
irdrop mv --- --- --- --- --- --- --- 0.006
holdpaths --- --- --- 0 0 0 --- 0
setuppaths --- --- --- 0 0 0 --- 0
macros --- --- 0 0 0 0 --- 0
cells --- 12625 12572 12966 12966 12966 --- 12966
registers --- 690 690 690 690 690 --- 690
buffers --- --- 0 394 394 394 --- 394
inverters --- --- 3210 3210 3210 3210 --- 3210
pins --- 354 354 354 354 354 --- 354
nets --- 16096 14841 15235 15235 15235 --- 15235
vias --- --- --- --- --- 92054 --- ---
wirelength um --- --- --- --- --- 32386.000 --- ---
memory B 266.035M 311.332M 619.660M 2.108G 648.195M 9.295G 616.000M 976.934M
exetime s 07.719 23.149 16.170 01:10.060 22.260 01:09.730 05.690 01:40.099
tasktime s 08.362 27.372 17.578 01:11.277 23.092 01:10.427 07.990 01:41.573
totaltime s 08.362 35.735 53.314 02:04.591 02:27.684 03:38.112 03:46.880 05:20.464
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Metrics for run_benchmark Tasks

Toggle import_verilog0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 60 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 266.035MB 07.719s 08.362s 08.362s
Toggle syn0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 119 --- --- --- 1416.855um^2 --- --- --- --- --- --- --- --- --- 12625 690 --- --- 354 16096 --- --- 311.332MB 23.149s 27.372s 35.735s
Toggle floorplan0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 41 --- --- 817 1383.960um^2 3531.570um^2 39.188% 0 0.001mw 0.001mw --- --- --- 0 12572 690 0 3210 354 14841 --- --- 619.660MB 16.170s 17.578s 53.314s
Toggle place0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 42 14 --- 817 1492.200um^2 3531.570um^2 42.253% 0 0.001mw 0.001mw --- 0 0 0 12966 690 394 3210 354 15235 --- --- 2.108GB 01:10.060s 01:11.277s 02:04.591s
Toggle cts0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 14 --- 817 1492.200um^2 3531.570um^2 42.253% 0 0.001mw 0.001mw --- 0 0 0 12966 690 394 3210 354 15235 --- --- 648.195MB 22.260s 23.092s 02:27.684s
Toggle route0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 147 0 817 1492.200um^2 3531.570um^2 42.253% 0 0.001mw 0.001mw --- 0 0 0 12966 690 394 3210 354 15235 92054 32386.000um 9.295GB 01:09.730s 01:10.427s 03:38.112s
Toggle write_gds0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 616.000MB 05.690s 07.990s 03:46.880s
Toggle write_data0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 121 --- 817 1492.200um^2 3531.570um^2 42.253% 0 0.001mw 0.001mw 0.006mv 0 0 0 12966 690 394 3210 354 15235 --- --- 976.934MB 01:40.099s 01:41.573s 05:20.464s
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